In the manufacture of semiconductors, several process steps are required to produce a functional die. A wafer of a starting material such as silicon or gallium arsenide is layered with oxide, poly, nitride, photoresist, and other materials in various configurations, depending on the type and design of the device which is being produced. Each step may require the local deposition, growth, or other formation of one of the above listed materials (patterning), or a blanket layer of the material may be laid down and a pattern etched away with chemicals or abraded away by particles. The etch step described may be a single etch step, or a series of etches.
In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate voltage level in spite of parasitic capacitances, noise, and leakage that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is also important as the density of DRAM arrays continue to increase for future generations of memory devices. The ability to densely pack storage cells while maintaining required storage capabilities is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured. One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, planar layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with interplate insulative layers having a high dielectric constant.
As shown in FIG. 1, the stacked capacitor design includes a substrate 10, source 12 and drain 14 regions, field 16 and gate 18 oxide, word lines 20 or "runners" (manufactured from pillars of poly 22, tungsten silicide 24, and oxide 26, for example), a layer of dielectric 28 such as tetraethyl orthosilicate overlying the word lines, a capacitor storage cell plate 30 interposed between every other pair of word lines 20, a top plate of the capacitor 32, digit (bit) lines 34, and various other dielectric layers 36. Other features which are not shown, such as P and N wells, may be necessary for proper functioning of the device and are easily determined by one of skill in the art.
As shown in FIG. 2 the cell plate is ideally formed by first laying down a patterned layer of photoresist 44 over a layer of poly 42. As shown in FIG. 3 the poly layer (as well as other exposed layers) is isotropically etched to isolate the cell plates 30.
As used herein, "anisotropic" etch refers to a directional etch in which the etch rate in one direction, usually vertically, greatly exceeds the etch rate in other directions. Directional etching is normally achieved by placing the wafer or substrate to be etched on a biased electrode. The applied bias acts to focus charged plasma particles down to the electrode in a substantially perpendicular direction. Advantages of anisotropic etching include reduced sidewall erosion and reduced undercutting. This contrasts with isotropic etching, wherein the removal of material is achieved at a more uniform rate over all exposed surfaces. The etch conventionally used to define the cell plates is a reactive ion etch (a "dry" etch). The speed and direction of the etch is affected by the energy (or pressure) imparted to the particles which bombard the exposed surfaces.
FIG. 3 shows the results of an ideal cell formation process using an anisotropic etch. Typically, however, the structure appears as shown in FIG. 4 after formation of the word lines 20, a layer of dielectric 28 over the word lines 20, the cell poly layer 42, and after depositing a layer of photoresist 40. Process etch steps leading to the FIG. 4 structure result in a retrograde sloping of the dielectric 28 as shown, especially with the use of tetraethyl orthosilicate (TEOS) which is commonly used.
A subsequent high pressure anisotropic plasma etch with a material such as chlorine (Cl.sub.2) forms the structure of FIG. 5. The high pressure etch undercuts 50 the poly storage plate 30 as shown and decreases its size and therefore its storage capacity. In addition to reducing the storage capacity of the cell, undercutting the poly can result in sharp points of poly which can shear off and cause unwanted shorts on the die surface.
To reduce the undercutting of the storage plate a low pressure plasma etch can be substituted for the high pressure etch. This, however, would leave the poly "stringers" 52 as shown in FIG. 5. The conductive poly stringers 52 which result from the low pressure etch can cause shorts between subsequently formed conductive layers, and are therefore undesirable. In addition to forming stringers, a low pressure etch requires a longer etch time which can reduce output.
Note that FIG. 5 is for description only, and shows the disadvantages of a high pressure etch (undercutting of the storage cell) and of a low pressure etch (the incomplete removal of the exposed poly to form stringers). A high pressure etch does not typically result in the unwanted poly stringers because the high pressure etch has relatively high isotropic properties due to the high kinetic energy imparted onto the etch particles. A low pressure etch would not typically result in the undercutting as shown because of the high anisotropic properties of a low pressure etch. Also, in a typically formed cell one of the word lines of FIGS. 2-5 would be formed over a layer of field oxide as can be determined from the structure of FIG. 1. An actual cell design which uses the invention can easily be determined from the description and Figures herein.
An etch process which maintains a high etch rate without undercutting and which removes the poly stringers between the word lines would be a desirable process.